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Numéro de sérieNAND512W3AZB1
CategorieMemory => Flash => NAND Flash
DescriptionNAND Flash Memory<<<>>>the NAND Flash 528 Byte/ 264 Word Page is A<<<>>>family of Non-volatile Flash Memories That Uses<<<>>>nand Cell Technology. The Devices Range From<<<>>>128Mbits to 1Gbit And Operate With Either a 1.8V<<<>>>or 3V Voltage Supply. The Size of a Page is Either<<<>>>528 Bytes (512 + 16 Spare) or 264 Words (256 + 8<<<>>>spare) Depending on Whether The Device Has a X8<<<>>>or X16 Bus Width.<<<>>>the Address Lines Are Multiplexed With The Data Input/<<<>>>output Signals on a Multiplexed x8 or X16 Input/<<<>>>output Bus. This Interface Reduces The Pin<<<>>>count And Makes it Possible to Migrate to Other<<<>>>densities Without Changing The Footprint.<<<>>>each Block CAN be Programmed And Erased Over<<<>>>100,000 Cycles. To Extend The LiFETime of NAND<<<>>>flash Devices it is Strongly Recommended to Implement<<<>>>an Error Correction Code (ECC). A Write<<<>>>protect Pin is Available to Give a Hardware Protection<<<>>>against Program And Erase Operations.<<<>>>the Devices Feature an Open-drain Ready/busy<<<>>>output That CAN be Used to Identify if The Program/<<<>>>erase/read (P/E/R) Controller is Currently Active.<<<>>>the Use of an Open-drain Output Allows The Ready/<<<>>>busy Pins From Several Memories to be Connected<<<>>>to a Single Pull-up Resistor.<<<>>>a Copy Back Command is Available to Optimize The<<<>>>management of Defective Blocks. When a Page<<<>>>program Operation Fails, The Data CAN be Programmed<<<>>>in Another Page Without Having to Resend<<<>>>the Data to be Programmed.
SociétéST Microelectronics, Inc.
DatasheetTélécharger NAND512W3AZB1 datasheet
 
 
  • Description courte
  • 128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories

    HIGH DENSITY NAND FLASH MEMORIES to 1 Gbit memory array to 32 Mbit spare area ­ Cost effective solutions for mass storage applications NAND INTERFACE or x16 bus width ­ Multiplexed Address/ Data ­ Pinout compatibility for all densities SUPPLY VOLTAGE ­ 1.8V device: VDD ­ 3.0V device: VDD to 3.6V PAGE SIZE ­ x8 device: + 16 spare) Bytes ­ x16 device: + 8 spare) Words BLOCK SIZE ­ x8 device: + 512 spare) Bytes ­ x16 device: + 256 spare) Words PAGE READ / PROGRAM ­ Random access: 12µs (max) ­ Sequential access: 50ns (min) ­ Page program time: 200µs (typ) COPY BACK PROGRAM MODE ­ Fast page copy without external buffering FAST BLOCK ERASE ­ Block erase time: 2ms (Typ) STATUS REGISTER ELECTRONIC SIGNATURE CHIP ENABLE `DON'T CARE' OPTION ­ Simple interface with microcontroller AUTOMATIC PAGE 0 READ AT POWER-UP OPTION ­ Boot from NAND support ­ Automatic Memory Download SERIAL NUMBER OPTION

    HARDWARE DATA PROTECTION ­ Program/Erase locked during Power transitions DATA INTEGRITY ­ 100,000 Program/Erase cycles ­ 10 years Data Retention DEVELOPMENT TOOLS ­ Error Correction Code software and hardware models ­ Bad Blocks Management and Wear Leveling algorithms ­ PC Demo board with simulation software ­ File System OS Native reference software ­ Hardware simulation models

    This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

    FEATURES SUMMARY. 1 Figure 1. Packages. 1 Table 1. Product List. 2 SUMMARY DESCRIPTION. 7 Table 2. Figure 2. Table 3. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Product Description. 8 Logic Diagram. 8 Signal Names. 8 Logic Block Diagram. 9 TSOP48 and WSOP48 Connections, x8 devices. 10 TSOP48 and WSOP48 Connections, x16 devices. 10 FBGA55 Connections, x8 devices (Top view through package). 11 FBGA55 Connections, x16 devices (Top view through package). 12 FBGA63 Connections, x8 devices (Top view through package). 13 FBGA63 Connections, x16 devices (Top view through package). 14

    MEMORY ARRAY ORGANIZATION. 15 Bad Blocks. 15 Table 4. Valid Blocks. 15 Figure 10.Memory Array Organization. 15 SIGNAL DESCRIPTIONS. 16 Inputs/Outputs (I/O0-I/O7). 16 Inputs/Outputs (I/O8-I/O15). 16 Address Latch Enable (AL). 16 Command Latch Enable (CL). 16 Chip Enable (E). 16 Read Enable (R). 16 Write Enable (W). 16 Write Protect (WP). 16 Ready/Busy (RB). 16 VDD Supply Voltage. 16 VSS Ground. 16 BUS OPERATIONS. 17 Command Input. 17 Address Input. 17 Data Input. 17 Data Output. 17 Write Protect. 17 Standby. 17 Table 5. Bus Operations. 17 Table 6. Address Insertion, x8 Devices. 18