ABCelectronique : portail d'information dans le domaine de l'électronique
 
 
Numéro de sérieAD9520-3
CategorieTiming Circuits => Clock Generators
DescriptionAD9520-4: 12 LVPECL/24 CMOS Output Clock Generator With Integrated 1.6 GHz VCO
The AD9520-41 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 1.4 GHz to 1.8 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz can also be used.

The AD9520 serial interface supports both SPI and I2C® ports. An in-package EEPROM can be programmed through the serial interface and store user-defined register setting for power-up and chip reset.
SociétéAnalog Devices
DatasheetTélécharger AD9520-3 datasheet
 
 
  • Description courte
  • 12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO AD9520-4
    FEATURES

    Low phase noise, phase-locked loop (PLL) On-chip VCO tunes from 1.4 GHz to 1.8 GHz Supports external 5 V VCO/VCXO to 2.4 GHz 1 differential or 2 single-ended reference inputs Accepts CMOS, LVDS, or LVPECL references to 250 MHz Accepts 16.67 MHz to 33.3 MHz crystal for reference input Optional reference clock doubler Reference monitoring capability Auto and manual reference switchover/holdover modes, with selectable revertive/nonrevertive switching Glitch-free switchover between references Automatic recover from holdover Digital or analog lock detect, selectable Optional zero delay operation Twelve 1.6 GHz LVPECL outputs divided into 4 groups Each group of 4 has a 1-to-32 divider with phase delay Additive output jitter as low 225 fS rms Channel-to-channel skew grouped outputs <16 ps Each LVPECL output can be configured as two CMOS outputs (for fOUT 250 MHz) Automatic synchronization of all outputs on power-up Manual synchronization of outputs as needed SPI- and I²C-compatible serial control port 64-lead LFCSP Nonvolatile EEPROM stores configuration settings

    APPLICATIONS

    Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation Broadband infrastructures

    The AD9520 serial interface supports both SPI and I2C® ports. An in-package EEPROM can be programmed through the serial interface and store user-defined register setting for power-up and chip reset. The AD9520 features 12 LVPECL outputs in four groups. Any of the 1.6 GHz LVPECL outputs can be reconfigured as two 250 MHz CMOS outputs. Each group of outputs has a divider that allows both the divide ratio (from to 32) and phase (coarse delay) to be set. The AD9520 is available a 64-lead LFCSP and can be operated from a single 3.3 V supply. The external VCO can have an operating voltage V. A separate output driver power supply can be from 3.465 V. The AD9520 is specified for operation over the standard industrial range to +85°C.

    The AD9520-41 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 1.4 GHz to 1.8 GHz. An external V/5 V VCO/VCXO to 2.4 GHz can also be used.

    The AD9520 is used throughout this data sheet to refer to all the members of the AD9520 family. However, when AD9520-4 is used, it is referring to that specific member of the AD9520 family.

    Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

    One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.

    Features.............................................................................................. 1 Applications....................................................................................... 1 General Description......................................................................... 1 Functional Block Diagram.............................................................. 1 Revision History............................................................................... 3 Specifications..................................................................................... 4 Power Supply Requirements....................................................... 4 PLL Characteristics...................................................................... 4 Clock Inputs.................................................................................. 7 Clock Outputs............................................................................... 7 Timing Characteristics................................................................ 8 Timing Diagrams..................................................................... 9 Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used)...................................................................... 10 Clock Output Absolute Phase Noise (Internal VCO Used).. 11 Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO)............................................................................. 11 Clock Output Absolute Time Jitter (Clock Cleanup Using Internal VCO)............................................................................. 11 Clock Output Absolute Time Jitter (Clock Generation Using External VCXO)......................................................................... 12 Clock Output Additive Time Jitter (VCO Divider Not Used)....................................................................................................... 12 Clock Output Additive Time Jitter (VCO Divider Used)..... 13 Serial Control Port--SPI Mode................................................ 13 Serial Control Port--I2C Mode................................................ 14 PD, SYNC, and RESET Pins..................................................... 15 Serial Port Setup Pins: SP0............................................... 15 LD, STATUS, REFMON Pins.................................................... 15 Power Dissipation....................................................................... 16 Absolute Maximum Ratings.......................................................... 17 Thermal Resistance.................................................................... 17 ESD Caution................................................................................ 17 Pin Configuration and Function Descriptions........................... 18 Typical Performance Characteristics........................................... 21 Terminology.................................................................................... 26 Detailed Block Diagram................................................................ 27 Theory of Operation...................................................................... 28 Operational Configurations...................................................... 28 Mode 0: Internal VCO and Clock Distribution................. 28 Mode 1: Clock Distribution or External VCO <1600 MHz................................................................... 30 Mode 2: High Frequency Clock Distribution--CLK or External VCO > 1600 MHz.................................................. 32 Phase-Locked Loop (PLL).................................................... 34 Configuration of the PLL...................................................... 34 Phase Frequency Detector (PFD)........................................ 34 Charge Pump (CP)................................................................. 35 On-Chip VCO........................................................................ 35 PLL External Loop Filter....................................................... 35 PLL Reference Inputs............................................................. 35 Reference Switchover............................................................. 36 Reference Divider R............................................................... 36 VCXO/VCO Feedback Divider A, B, R..................... 36 Digital Lock Detect (DLD)................................................... 38 Analog Lock Detect (ALD)................................................... 38 Current Source Digital Lock Detect (CSDLD).................. 38 External VCXO/VCO Clock Input (CLK/CLK)................ 39 Holdover.................................................................................. 39 Manual Holdover Mode........................................................ 39 Automatic/Internal Holdover Mode.................................... 39 Frequency Status Monitors................................................... 41 VCO Calibration.................................................................... 42 Zero Delay Operation................................................................ 43 Internal Zero Delay Mode..................................................... 43 External Zero Delay Mode.................................................... 43 Clock Distribution..................................................................... 44 Operation Modes................................................................... 44 CLK or VCO Direct-to-LVPECL Outputs.......................... 44 Clock Frequency Division..................................................... 45 VCO Divider........................................................................... 45 Channel Dividers................................................................... 45 Synchronizing the Outputs--SYNC Function................... 47 LVPECL Output Drivers....................................................... 48 CMOS Output Drivers.......................................................... 49 Reset Modes................................................................................ 49 Power-On Reset...................................................................... 49 Hardware Reset via the RESET Pin..................................... 49 Soft Reset via the Serial Port................................................. 49 Soft Reset to Settings in EEPROM when EEPROM Pin = 0 via the Serial Port......................................................................... 49

    Power-Down Modes...................................................................49 Chip Power-Down via PD.....................................................49 PLL Power-Down....................................................................50 Distribution Power-Down.....................................................50 Individual Clock Output Power-Down................................50 Individual Clock Channel Power-Down.............................50 Serial Control Port..........................................................................51 SPI/I2C Port Selection................................................................51 I2C Serial Port I C Bus Characteristics...........................................................51

    EEPROM Operations..................................................................... 58 Writing to the EEPROM............................................................ 58 Reading from the EEPROM...................................................... 58 Programming the EEPROM Buffer Segment.......................... 59 Register Section Definition Group....................................... 59 IO_UPDATE (Operational Code 0x80).............................. 59 End-of-Data (Operational Code 0xFF)............................... 59 Pseudo-End-of-Data (Operational Code 0xFE)................. 59 Thermal Performance..................................................................... 61 Register Map.................................................................................... 62 Register Map Descriptions............................................................. 67 Applications Information............................................................... 82 Frequency Planning Using the AD9520.................................. 82 Using the AD9520 Outputs for ADC Clock Applications.... 82 LVPECL Clock Distribution...................................................... 82 CMOS Clock Distribution......................................................... 83 Outline Dimensions........................................................................ 84 Ordering Guide........................................................................... 84

    Data Transfer Process.............................................................52 Data Transfer Format.............................................................53 I2C Serial Port Timing............................................................53 SPI Serial Port Operation...........................................................54 Pin Descriptions......................................................................54 SPI Mode Operation...............................................................54 Communication Cycle--Instruction Plus Write.........................................................................................54 Read..........................................................................................54 SPI Instruction Word (16 Bits)..................................................55 SPI MSB/LSB First Transfers.....................................................55