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Numéro de sérieESD9X7.0
CategorieDiscrete => Diodes & Rectifiers => Protection
DescriptionSOD-923 ESD PROTECTION
The ESD9X Series is designed to protect voltage sensitive components from ESD. Excellent clamping capability, low leakage, and fast response time provide best in class protection on designs that are exposed to ESD. Because of its small size, it is suited for use in cellular phones, MP3 players, digital cameras and many other portable applications where board space is at a premium
SociétéON Semiconductor
DatasheetTélécharger ESD9X7.0 datasheet
 
 
  • Description courte
  • The ESD9X Series is designed to protect voltage sensitive components from ESD. Excellent clamping capability, low leakage, and fast response time provide best in class protection on designs that are exposed to ESD. Because of its small size, it is suited for use in cellular phones, MP3 players, digital cameras and many other portable applications where board space at a premium.

    · Low Clamping Voltage· Small Body Outline Dimensions:·

    x 0.60 mm) Low Body Height: 0.017 (0.43 mm) Max Stand-off Voltage: 12 V Low Leakage Response Time is Typically 1 ns ESD Rating of Class 3 16 kV) per Human Body Model IEC61000-4-2 Level 4 ESD Protection These are Pb-Free Devices

    Mechanical Characteristics: CASE: Void-free, transfer-molded, thermosetting plastic
    Epoxy Meets 94 V-0 LEAD FINISH: 100% Matte Sn (Tin) MOUNTING POSITION: Any

    For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Unit mW °C

    See specific marking information in the device marking column of the table on page 2 of this data sheet.

    Per Human Body Model Per Machine Model PD TJ, Tstg TL

    Total Power Dissipation on FR-5 Board (Note = 25°C Junction and Storage Temperature Range Lead Solder Temperature - Maximum (10 Second Duration)

    Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. x 0.62 in.

    See Application Note AND8308/D for further description of survivability specs.

    (TA = 25°C unless otherwise noted) Symbol IPP VC VRWM IR VBR IF VF Ppk C Parameter Maximum Reverse Peak Pulse Current Clamping Voltage @ IPP Working Peak Reverse Voltage Maximum Reverse Leakage Current @ VRWM Breakdown Voltage @ IT Test Current Forward Current Forward Voltage @ IF Peak Power Dissipation Max. Capacitance @VR = 0 and = 1 MHz IPP VC VBR VRWM IF I

    *See Application Note AND8308/D for detailed explanations of datasheet parameters.
    ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted, 1.1 V Max. 10 mA for all types)

    VRWM (V) Device* ESD9X7.0ST5G ESD9X12ST5G Device Marking 5** C Max IR (mA) @ VRWM Max VBR (V) @ IT (Note 2) Min Max IPP (A) (Note 3) VC (V) @ Max IPP (Note 3) Max Ppk (W) x 20 ms) Typ C (pF) Typ Figures 1 and 2 (Note 5)

    *Other voltages available upon request. **Rotated 270 degrees. 2. VBR is measured with a pulse test current at an ambient temperature 25°C. 3. Surge current waveform per Figure 5. 4. For test procedure see Figures 3 and 4 and Application Note 5. ESD9X5.0ST5G shown below. Other voltages available upon request.

    Figure 1. ESD Clamping Voltage Screenshot Positive 8 kV contact per IEC 61000-4-2
    Figure 2. ESD Clamping Voltage Screenshot Negative 8 kV contact per IEC 61000-4-2

    Figure 4. Diagram of ESD Test Setup The following is taken from Application Note AND8308/D - Interpretation of Datasheet Parameters for ESD Devices. ESD Voltage Clamping

    For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000-4-2 waveform. Since the IEC61000-4-2 was written as a pass/fail spec for larger

    systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D.

    PEAK VALUE IRSM 8 ms PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY 8 ms HALF VALUE 20 ms