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Numéro de sériePGA117
CategorieAnalog & Mixed-Signal Processing => Amplifiers => PGA (Programmable Gain Amplifiers)
DescriptionZero-Drift, Programmable Gain Amplifier With MUX
The PGA112 and PGA113 (binary/scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in an MSOP-10 package. The PGA116 and PGA117 (binary/scope gains) offer 10 analog inputs, a four-pin SPI interface with daisy-chain capability, and hardware and software shutdown in a TSSOP-20 package.

All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9VCAL, 0.1VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200
SociétéTexas Instruments, Inc.
DatasheetTélécharger PGA117 datasheet
 
 
  • Description courte

  • FEATURES

    Rail-to-Rail Input/Output Offset: 25µV (typ), 100µV (max) Zerø Drift: 0.35µV/°C (typ), 1.2µV/°C (max) Low Noise: 12nV/Hz Input Offset Current: ±5nA max (+25°C) Gain Error: 0.1% max 32), 0.3% max > 32) Binary Gains: (PGA112, PGA116) Scope Gains: (PGA113, PGA117) Gain Switching Time: 200ns Two Channel MUX: PGA113 10 Channel MUX: PGA116, PGA117 Four Internal Calibration Channels Amplifier Optimized for Driving CDAC ADCs Output Swing: 50mV to Supply Rails AVDD and DVDD for Mixed Voltage Systems = 1.1mA (typ) Software/Hardware Shutdown: IQ 4µA (typ) Temperature Range: to +125°C SPITM Interface (10MHz) with Daisy-Chain Capability

    APPLICATIONS

    · Remote e-Meter Reading Automatic Gain Control Portable Data Acquisition PC-Based Signal Acquisition Systems Test and Measurement Programmable Logic Controllers Battery-Powered Instruments Handheld Test Equipment

    DESCRIPTION

    The PGA112 and PGA113 (binary/scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown an MSOP-10 package. The PGA116 and PGA117 (binary/scope gains) offer 10 analog inputs, a four-pin SPI interface with daisy-chain capability, and hardware and software shutdown a TSSOP-20 package. All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9VCAL, 0.1VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: and 128; scope gains are: and 200.

    CAL3 CAL4 VREF RI SPI Interface 8 9 SCLK DIO CS RF MUX Output Stage 5 VOUT

    Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola. All other trademarks are the property of their respective owners.

    PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

    This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

    DEVICE # OF MUX INPUTS Two 10 GAINS (Eight Each) Binary Scope Binary Scope SPI DAISY-CHAIN No ü SHUTDOWN HARDWARE No ü SOFTWARE PACKAGE MSOP-10 TSSOP-20

    PRODUCT (2) (3) DESCRIPTION (Gains/Channels) Binary (2)/2 Channels Scope (3)/2 Channels Binary /10 Channels Scope (3)/10 Channels

    For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Binary gains: and 128. Scope gains: and 200.

    Over operating free-air temperature range, unless otherwise noted.

    PGA116, PGA117 Supply Voltage Signal Input Terminals, Voltage (2) Signal Input Terminals, Current Output Short-Circuit Operating Temperature Storage Temperature Junction Temperature Human Body Model (HBM) ESD Ratings: Charged Device Model (CDM) Machine Model (MM) (1) (2)

    Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails should be current limited 10mA or less.

    Boldface limits apply over the specified temperature range, = 100pF connected to DVDD/2, and VREF = GND, unless otherwise noted.

    PGA116, PGA117 PARAMETER OFFSET VOLTAGE Input Offset Voltage VOS AVDD = DVDD = +5V, VREF = VIN = AVDD/2, VCM = 2.5V AVDD = DVDD = +5V, VREF = VIN = AVDD/2, VCM 4.5V vs Temperature, +125°C vs Temperature, +85°C vs Temperature, +125°C vs Temperature, +85°C vs Power Supply Over Temperature, to +125°C INPUT ON-CHANNEL CURRENT Input On-Channel Current (Ch0, Ch1) Over Temperature, to +125°C INPUT VOLTAGE RANGE Input Voltage Range (1) Overvoltage Input Range INPUT IMPEDANCE (Channel On) (3) Channel Input Capacitance Channel Switch Resistance Amplifier Input Capacitance Amplifier Input Resistance VCAL/CH0 GAIN SELECTIONS Nominal Gains Binary gains: Scope gains: DC Gain Error 50 DC Gain Drift CAL2 DC Gain Error

    AVDD = DVDD = +5V, VCM = 2.5V AVDD = DVDD = +5V, VCM = 2.5V AVDD = DVDD = +5V, VCM = 4.5V AVDD = DVDD = +5V, VCM = 4.5V

    AVDD = DVDD to +5.5V, VCM = 0.5V, VREF = VIN = AVDD/2 AVDD = DVDD to +5.5V, VCM = 0.5V, VREF = VIN = AVDD/2

    VOUT = GND 85mV to DVDD ­ 85mV VOUT = GND 85mV to DVDD ­ 85mV VOUT = GND 85mV to DVDD ­ 85mV VOUT = GND 85mV to DVDD ­ 85mV VOUT = GND 85mV to DVDD ­ 85mV VOUT = GND 85mV to DVDD 85mV Op Amp + Input = 0.9VCAL, VREF = VCAL 1 Op Amp + Input = 0.9VCAL, VREF = VCAL 1 Op Amp + Input = 0.1VCAL, VREF = VCAL 1 Op Amp + Input = 0.1VCAL, VREF = VCAL = 1

    CAL2 DC Gain Drift CAL3 DC Gain Error CAL3 DC Gain Drift (4) INPUT IMPEDANCE (Channel Off) (3) Input Impedance INPUT OFF-CHANNEL CURRENT Input Off-Channel Current Ch1) (5) Over Temperature, to +125°C Channel-to-Channel Crosstalk ILKG CCH

    VREF = GND, VOFF-CHANNEL = AVDD/2, VON-CHANNEL ­ 0.1V VREF = GND, VOFF-CHANNEL = AVDD/2, VON-CHANNEL ­ 0.1V

    Gain error is a function of the input voltage. Gain error outside of the range (GND + 85mV VOUT DVDD ­ 85mV) increases to 0.5% (typical). Input voltages beyond this range must be current limited < |10mA| through the input protection diodes on each channel to prevent permanent destruction of the device. See Figure 1. Total VOUT error must be computed using input offset voltage error multiplied by gain. Includes op amp = 1 error. Maximum specification limitation limited by final test time and capability.