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Numéro de sérieTMS320C6745
CategorieDSPs (Digital Signal Processors)
DescriptionFloating-Point Digital Signal Processor
The C6745/6747 is a Low-power applications processor based on C674x™ DSP core. It provides significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The C6745/6747 enables OEMs and ODMs to quickly bring to market devices featuring high processing performance.

The C6745/6747 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256KB memory space that is shared between program and data space. L2 also has a 1024KB ROM. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an additional 128KB RAM shared memory is available for use by other hosts without affecting DSP performance.
SociétéTexas Instruments, Inc.
DatasheetTélécharger TMS320C6745 datasheet
 
 
  • Description courte

  • · Applications ­ Industrial Control ­ USB, Networking ­ High-Speed Encoding ­ Professional Audio Software Support ­ TI DSP/BIOSTM ­ Chip Support Library and DSP Library 300-MHz C674xTM VLIW DSP C674x Instruction Set Features ­ Superset of the C67x+TM and C64x+TM ISAs 2400/1800 C674x MIPS/MFLOPS ­ Byte-Addressable (8-/16-/32-/64-Bit Data) ­ 8-Bit Overflow Protection ­ Bit-Field Extract, Set, Clear ­ Normalization, Saturation, Bit-Counting ­ Compact 16-Bit Instructions C674x Two Level Cache Memory Architecture 32K-Byte L1P Program RAM/Cache 32K-Byte L1D Data RAM/Cache 256K-Byte L2 Unified Mapped RAM/Cache ­ Flexible RAM/Cache Partition (L1 and 1024K-Byte L2 ROM Enhanced Direct-Memory-Access Controller ­ 2 Transfer Controllers ­ 32 Independent DMA Channels ­ 8 Quick DMA Channels ­ Programmable Transfer Burst Size TMS320C674xTM Floating Point VLIW DSP Core ­ Load-Store Architecture With Non-Aligned Support ­ 64 General-Purpose Registers (32 Bit) ­ Six ALU (32-/40-Bit) Functional Units· Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point· Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks· Supports up to Two Floating Point (SP or DP) Approximate Reciprocal or Square Root Operations Per Cycle ­ Two Multiply Functional Units Mixed-Precision IEEE Floating Point Multiply Supported up to: x SP Per Clock SP DP Every Two Clocks x DP Every Three Clocks x DP Every Four Clocks· Fixed Point Multiply Supports Two x 32-Bit Multiplies, Four x 16-Bit Multiplies, or Eight x 8-Bit Multiplies per Clock Cycle, and Complex Multiples ­ Instruction Packing Reduces Code Size ­ All Instructions Conditional ­ Hardware Support for Modulo Loop Operation ­ Protected Mode Operation ­ Exceptions Support for Error Detection and Program Redirection 128K-Byte RAM Shared Memory Two External Memory Interfaces: ­ EMIFA· NOR (8-/16-Bit-Wide Data)· NAND (8-/16-Bit-Wide Data)· 16-Bit SDRAM With 128MB Address Space ­ EMIFB· or 16-Bit SDRAM With 256MB Address Space Three Configurable 16550 type UART Modules: ­ UART0 With Modem Control Signals ­ 16-byte FIFO or 13x Oversampling Option LCD Controller Two Serial Peripheral Interfaces (SPI) Each With One Chip-Select Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO) Two Master/Slave Inter-Integrated Circuit (I2C BusTM) USB 1.1 OHCI (Host) With Integrated PHY (USB1) USB 2.0 OTG Port With Integrated PHY (USB0) ­ USB 2.0 High-/Full-Speed Client ­ USB 2.0 High-/Full-/Low-Speed Host ­ End Point 0 (Control)·

    Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. TMS320C6000, C6000 are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.

    PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

    ­ End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) Rx and Tx Three Multichannel Audio Serial Ports: ­ Transmit/Receive Clocks to 50 MHz ­ Six Clock Zones and 28 Serial Data Pins ­ Supports TDM, I2S, and Similar Formats ­ DIT-Capable (McASP2) ­ FIFO buffers for Transmit and Receive 10/100 Mb/s Ethernet MAC (EMAC): ­ IEEE 802.3 Compliant (3.3-V I/O Only) ­ RMII Media Independent Interface ­ Management Data I/O (MDIO) Module One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address/Data Bus For High Bandwidth Real-Time Clock With 32 KHz Oscillator and Separate Power Rail One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers) One 64-Bit General-Purpose Timer (Watch Dog) Three Enhanced Pulse Width Modulators (eHRPWM):

    ­ Dedicated 16-Bit Time-Base Counter With Period And Frequency Control ­ 6 Single Edge, 6 Dual Edge Symmetric or 3 Dual Edge Asymmetric Outputs ­ Dead-Band Generation ­ PWM Chopping by High-Frequency Carrier ­ Trip Zone Input Three 32-Bit Enhanced Capture Modules (eCAP): ­ Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) outputs ­ Single Shot Capture up to Four Event Time-Stamps Two 32-Bit Enhanced Quadrature Encoder Pulse Modules (eQEP) C6747 Device: ­ 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch C6745 Device ­ 176-Pin Thin Quad Flat Pack (TQFP) [PTP Suffix], 0.5-mm Pin Pitch Commercial or Extended Temperature

    DSP/BIOS, TMS320, TMS320C62x, and TMS320C67x are trademarks of Texas Instruments. All trademarks are the property of their respective owners.