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Numéro de sérieXR16M670
CategorieCommunication => UARTs
Description1.62V To 3.63V Single UART With 32-Byte FIFO
The XR16M670¹ (M670) is an enhanced quad Universal Asynchronous Receiver and Transmitter (UART) each with 32 bytes of transmit and receive FIFOs, programmable transmit and receive FIFO trigger levels, automatic hardware and software flow control, and data rates of up to 16 Mbps at 4X sampling rate. Each UART has a set of registers that provide the user with operating status and control, receiver error indications, and modem serial interface controls. An internal loopback capability allows onboard diagnostics. The M670 is available in a 24-pin QFN, 32-pin QFN and 25-pin BGA packages. The M670 packages only offer the 16 mode interface. The XR16M670 is compatible with the industry standard XR16L570
SociétéSipex Corporation
DatasheetTélécharger XR16M670 datasheet
 
 
  • Description courte

  • The is an enhanced Universal Asynchronous Receiver and Transmitter (UART) with 32 bytes of transmit and receive FIFOs, selectable transmit and receive FIFO trigger levels, automatic hardware and software flow control, and data rates to 16 Mbps 3.3V, 12.5 Mbps at 2.5V and 7.5 Mbps at 1.8V with 4X data sampling rate. The Auto RS-485 Half-Duplex Direction control feature simplifies both the hardware and software for half-duplex RS-485 applications. In addition, the Multidrop mode with Auto Address detection increases the performance by simplifying the software routines. The Independent TX/RX Baud Rate Generator feature allows the transmitter and receiver to operate at different baud rates. Power consumption of the M670 can be minimized by enabling the sleep mode and PowerSave mode. The M670 has a 16550 compatible register set that provide users with operating status and control, receiver error indications, and modem serial interface controls. An internal loopback capability allows onboard diagnostics. The M670 is available in 24-pin QFN, 32-pin QFN and 25-pin BGA packages. All three packages offer the 16 mode (Intel bus) interface only.

    FEATURES

    · Intel data bus Interface· 16 Mbps maximum data rate· Selectable TX/RX FIFO Trigger Levels· TX/RX FIFO Level Counters· Independent TX/RX Baud Rate Generator· Fractional Baud Rate Generator· Auto RTS/CTS Hardware Flow Control· Auto XON/XOFF Software Flow Control· Auto RS-485 Half-Duplex Direction Control· Multidrop mode w/ Auto Address Detect· Sleep Mode with Automatic Wake-up· PowerSave mode in 24-pin QFN package· Infrared (IrDA 1.0 and 1.1) mode· to 3.63V supply operation· Crystal oscillator or external clock input

    APPLICATIONS

    · Personal Digital Assistants (PDA)· Cellular Phones/Data Devices· Battery-Operated Devices· Global Positioning System (GPS)· Bluetooth

    Exar Corporation 48720 Kato Road, Fremont CA, (510) 668-7000· FAX (510) 668-7017· www.exar.com

    TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO FIGURE 2. PIN OUT ASSIGNMENT FOR 24-PIN QFN, 32-PIN QFN AND 25-BGA PACKAGES

    A1 Corner Transparent Top View CTS# VCC D3 D4 RESET DTR# D1 D2 INT RTS# A1 A0 DSR# CS# RX A2 IOR# IOW# XTAL1 GND 4 5

    PART NUMBER XR16M670IL32 XR16M670IB25 PACKAGE 24-Pin QFN 32-Pin QFN 25-Pin BGA OPERATING TEMPERATURE RANGE to +85°C DEVICE STATUS Active

    NAME 24-QFN PIN# 32-QFN PIN# 25-BGA PIN# TYPE DESCRIPTION

    DATA BUS INTERFACE D1 D0 IOR# B5 I Address lines [2:0]. These 3 address lines select the internal registers in UART during a data bus transaction. Data bus lines [7:0] (bidirectional).

    This input is read strobe (active low). The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [A2:A0], puts the data byte on the data bus to allow the host processor to read it on the rising edge. This input is write strobe (active low). The falling edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. This input is chip select (active low) to enable the device.

    O This output is the active high device interrupt output. The output (OD) state is defined by the user through the software setting of MCR[3]. INT is set to the active mode when MCR[3] is set to a logic 1. INT is set to the three state mode when MCR[3] is set to a logic 0. See MCR[3].

    MODEM OR SERIAL I/O INTERFACE D3 O UART Transmit Data or infrared encoder data. Standard transmit and receive interface is enabled when 0. In this mode, the TX signal will be a logic 1 during reset or idle (no data). Infrared IrDA transmit and receive interface is enabled when 1. In the Infrared mode, the inactive state (no data) for the Infrared encoder/decoder interface is a logic it is not used, leave it unconnected. UART Receive Data or infrared receive data. Normal receive data input must idle at logic 1 condition. The infrared receiver idles at logic 0. This input should be connected to VCC when not used. UART Request-to-Send (active low) or general purpose output. This output must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1] and IER[6]. UART Clear-to-Send (active low) or general purpose input. It can be used for auto CTS flow control, see EFR[7], MSR[4] and IER[7]. This input should be connected to VCC when not used. UART Data-Terminal-Ready (active low) or general purpose output.